ABSTRACT

Testing of circuits with external testing equipment is becoming very difficult due to the manual interface between the VLSI design and performance of the external tester. Hence, external testers are less efficient due to increasing cost and high yield loss which causes inherent testing accuracies. To overcome the inaccuracies caused by the external testers, the processor should empower to test by itself. Hardware based built in self-testing methodologies have many drawbacks due low performance issues and inabilities in structural testing to generate random test patterns with low fault coverage.

Software based built in self-testing methods are under review and are being developed in the research field to overcome the problems with the hardware testing equipment. In this process of testing, programmable cores are used for software based built in self-testing on processors for generating test patterns as inputs for testing to analyse the output response and also to detect and diagnose the faults present in the processor.  Once the programmable core tests itself on the processor, it can be used again for testing buses and global interconnects and other non-programmable IP cores.[1] The benefits of this techniques are at- speed testing, high performance testing, low yield loss, high fault coverage, low cost modelling, less hardware utilization and easy generation of random test patterns. In this paper, we give a literature survey of the techniques which can be applied on circuits and challenges emerging in the software based built in self testing paradigm.

1.0 INTRODUCTION

Usage of testing circuits on recent VLSI Chips has many drawbacks with respect to yield, time, speed and cost. Recently used testing circuits cannot be relied upon due to the increasing complexity and decreasing size of the chips. The current testing circuits cannot be used on the upcoming new circuits due to rapid variation of speed and performance between the circuits and testers. Software based built in self testing is implemented on machines rather than computers. The industries these days, install the self-testing software in the devices or machines to control and manage by itself. Mostly, the embedded software is specially designed for a typical hardware design. There are different types of embedded software used for complex hardware which, need the requirement of crucial development of software based built in self testing. Hence, Embedded Software Developers are developing automatic testing tools to test and detect the faults in the chips. The main motivation behind this research is to increase the efficiency of testing by controlling the increasing yield loss to an acceptable rate. To overcome the above issues, a software based built in self testing equipment will be proposed.[6]

The architecture of SOCs has been widely used due to a large number of components present in a single silicon chip such as ADC, DAC, mixed signals, RF signals and systems such as micromechanical on a single silicon chip. The programming abilities of SOCs along with its architecture with high operating frequencies and change in the technology is improvising the VLSI testing methodologies. Due to the growing gap between the performance of the external tester and the speed of the device, there are many challenges faced by the external testers such as high yield loss which cause errors in the output response and lead to loss of good chips, high speed external testers are not cost efficient as they are very costly, mixed signal testing with analogue components cannot be tested on a digital logic tester and vice versa. And also, testing a mixed signal component with a mixed signal chip would be a very expensive form of VLSI testing.

Software based built in self testing techniques eliminate the requirements of external testers and has the provision to apply the input test signal and analyse the output response with at speed which provide good precision than the external tester. Already existing built in self testing methodologies use the structural form of testing techniques. The scan based built in self testing methodologies is a form of the structural built in self testing which provides good quality test results and depends on a dedicated hardware circuit for testing. Due to the dedicated hardware circuit dependency in testing, there is an area, performance and time overhead. Structural built in self testing applies structural random testing patterns which cause increase in power consumption compared to normal system operations. [3]Also, existing external testers follow structural built in self testing methodologies which lead to difficulty in diagnosing and detecting time related faults. In addition, the existing structural built in self testing techniques require the solutions to resolve the problems related to various timing issues.

A new software based built in self testing equipment can overcome the problems occurring in the external testers and hardware based built in self testing. The software based built in self testing consists of programmable cores on the processor which first tests itself by compiling and executing an automatically synthesised random test program which can diagnose and detect high fault coverage. The software based built in self testing technique uses the structural random testing pattern as its strategy in the VLSI design environment. Hence, this eliminates the problems caused by the functional testing patterns in the VLSI design environment. Then, the programmable core generates the random testing pattern and also analyses the output response of processors on busses and global interconnects and other non-programmable IP cores. This technique is also known as structural built in self testing.

The concept on software based built in self testing is illustrated in Figure 1 using busses and global interconnects on the processor. The non-programmable IP cores in the processor are connected to A PCI bus and global interconnect via VCI. The Virtual Component Interface establishes a communication between the non-programmable IP core and the bus and global interconnect. Firstly, the chip tests its