Can a CISC instruction set be RISC under such a definition?

Load a single byte from memory
March 21, 2023
Discuss alternative ways of implementing 8-bit and 16-bit object access
March 21, 2023

Can a CISC instruction set be RISC under such a definition?

1993 Paper 7 Question 3
Comparative Architectures
A revisionist view might be that a processor design is RISC if every transistor pays
its way in terms of global system performance, i.e. the design is in some sense a
local optimum. Explain how this view relates to the original definition of RISC.
Can a CISC instruction set be RISC under such a definition? [4 marks]
Given a certain silicon budget (e.g. 106
transistors) compare and contrast, under the
above criterion, alternative ways of spending the excess over the (say) 104
transistor
cost of a simple load-store one-accumulator machine. You might find it helpful to
consider the various features and instructions of common processors. [12 marks]
This budget is sufficient to build most, but not all, of a VAX. Which parts would
you omit and how could you arrange to execute full VAX code? [4 marks]