Describe the Translation Lookaside Buffer (TLB) architecture

Discuss the pros and cons of architectures with a 64-bit word size versus those with a 32-bit word size
March 21, 2023
The IA-64 architecture
March 21, 2023

Describe the Translation Lookaside Buffer (TLB) architecture

2005 Paper 8 Question 1
Comparative Architectures
(a) All modern processors provide support for memory access protection and
translation. Describe the Translation Lookaside Buffer (TLB) architecture
of a modern microprocessor, and hence what information a typical TLB entry
would contain. [6 marks]
(b) Some architectures are described as having software-managed TLBs, whereas
others have entries loaded entirely by hardware. Describe and contrast the
two approaches. [6 marks]
(c) Why might a TLB that supports “superpages” (entries that cover multiple
pages) benefit applications that use lots of memory? What steps must the
operating system take to enable superpages to be used? [4 marks]
(d) Even hardware-filled TLBs usually rely on software to determine when
entries should be invalidated. How might you design a hardware solution
to automatically keep the TLB coherent with OS pagetables? What extra
complications would Symmetric Multiprocessor Systems (SMP) pose?
[4 marks]