What features of a processor’s instruction set are desirable if a pipelined implementation is planned?

Imagine two processor implementations with equal performance
March 21, 2023
What features of a bus does a snoopy cache coherence protocol depend on?
March 21, 2023

What features of a processor’s instruction set are desirable if a pipelined implementation is planned?

COMPUTER SCIENCE TRIPOS Part II – 2017 – Paper 7
Comparative Architectures (RDM)
(a) What features of a processor’s instruction set are desirable if a pipelined
implementation is planned? [5 marks]
(b) The performance of a processor typically improves when a modest number of
pipeline stages are created. Why does it become difficult to maintain near linear
performance gains with deeper pipelines? [5 marks]
(c) Clustered superscalar processors partition functional units into clusters. Data
forwarding within a cluster operates as normal allowing dependent instructions
to execute on consecutive clock cycles. Communication between clusters
normally incurs an additional delay of 1 or 2 clock cycles. The clustering
idea may also be extended to include the issue buffer (also known as the issue
window).
(i) What problem does clustering attempt to solve? [5 marks]
(ii) Assume a processor has two symmetric clusters that contain both functional
units and an issue buffer. In this processor, instructions must be steered
to a particular cluster before they are inserted in an issue buffer. What
should the two basic goals of a good steering policy be? [5 marks]