1999 Paper 7 Question 3 Comparative Architectures Why might a processor supporting “dynamic execution” (out-of-order execution with speculation) yield better performance than a statically-scheduled processor with […]
1999 Paper 8 Question 4 Comparative Architectures A new microprocessor has a 64 Kbyte write-back L1 D-cache that is 2-way set-associative (employing a random replacement policy) […]
1998 Paper 8 Question 4 Comparative Architectures Modern workstations typically have memory systems that incorporate two or three levels of caching. Explain why they are designed […]
1997 Paper 7 Question 3 Comparative Architectures You are a computer architect working on the design of your company’s new instruction set architecture for the 21st […]